The present invention relates to the manufacture of semiconductor products in general, and particularly to protection against damage to semiconductor circuits from effects of electromagnetic wave energy generated during an etch process.
During the manufacture of semiconductor products, layers of material are laid down or grown. Some layers are then etched, to produce the desired shapes of transistors, metal lines, and other microelectronics devices. When the processing has finished, a functioning chip is produced. If the chip contains a memory array, it typically has a plurality of memory transistors that may be programmed or erased. For example, the memory transistors may be floating gate transistors, nitride read only memory (NROM) transistors, silicon oxide-nitride oxide-silicon (SONOS) transistors, and any other non-volatile memory metal oxide semiconductor (MOS) devices capable of storing charge. Unfortunately, the manufacturing process may have some undesirable side effects. For example, in MOS technology, the charging of active elements during the manufacturing process may alter the device""s characteristics or even damage them.
Reference is now made to FIG. 1, which illustrates a typical cross-section of an MOS or complementary MOS (CMOS) transistor wafer. It is typically formed of a gate oxide 10 over which is a polysilicon element 12. On either side of the gate oxide 10 are field oxide 14 which are much thicker than the gate oxide 10. Typically, the polysilicon element 12 also spreads over the field oxides 14. A more advanced process may have trench isolation instead of field oxides, but the effects discussed hereinbelow are the same in such a case.
During manufacture, the field oxides 14 are first produced on a substrate 8, after which the gate oxides 10 are grown. A layer of polysilicon is laid over the oxides 10 and 14, and then etched to the desired shapes, such as by employing a shaped photoresist layer 15. The etching process typically involves placing a plasma 16, as is now explained.
The etching process may be carried out by many methods, however, plasma based processes such as plasma enhanced chemical vapor deposition (CVD) and reactive ion etching (RIE) are very common. Typically, energy for etching is generated by coupling radio frequency (RF) electromagnetic energy to a plasma 16. The RF energy may be supplied by an RF generator coupled to a power supply. In FIG. 1, the etching process involves placing plasma 16 between the transistor and a electrified plate 18 connected to a high voltage source, and electrically connecting a second electrified plate 20 to the substrate 8.
Plasma may generate ultraviolet (UV) photons. UV photons may also be generated during deposition of metal layers, such as in sputtering techniques. High energy electrons associated with the UV photons may charge the transistor. More specifically, since polysilicon is a conductive material, the polysilicon element 12 may become charged by the high energy photons. This is known as the xe2x80x9ccharging effectxe2x80x9d. The charging effect is not generally a problem in conventional floating gate transistors because the excess charge may be erased. However, it may degrade the gate oxide as is now explained.
The more charge the polysilicon element 12 attracts, the greater the voltage drop between the polysilicon element 12 and the substrate 8. If the voltage drop is high enough, it induces Fowler-Nordheim (F-N) tunneling of charge from the substrate 8 to the polysilicon element 12, via the gate oxide 10, as indicated by arrows 24. Since the field oxides 14 are quite thick, no F-N tunneling generally occurs through them. Unfortunately, F-N tunneling may cause breakdown of the gate oxide 10, especially if the gate oxide 10 is quite thin. It is appreciated that, once the gate oxide 10 has broken down, the transistor will not function.
Solutions are known for handling the gate oxide degradation problem of CMOS and floating gate transistors. The extent of the F-N tunneling is a function of the size of the polysilicon element 12, the area of the gate oxide 10 and its thickness. As long as the area of polysilicon over the field oxides 14 is no larger than K times the area over the thin gate oxides 10 (where K, called the xe2x80x9cantenna ratioxe2x80x9d, varies according to the specific manufacturing process), the F-N tunneling will not occur. Alternatively, the total charge passing through the oxide will be small enough not to cause breakdown of the oxide. Accordingly, the amount of F-N tunneling may be reduced by reducing the area of the field oxide relative to the area of the gate.
In NROM devices, similar to the CMOS and floating gate memory devices, the abovementioned charging effect may be reduced by various techniques, such as the reduction of the antenna ratio K and adding discharge devices along the poly lines. Such techniques are discussed in applicant/assignee""s U.S. patent application Ser. No. 09/336,666, filed Jun. 18, 1999 and entitled xe2x80x9cMethod and Circuit for Minimizing the Charging Effect During Manufacture of Semiconductor Devicesxe2x80x9d, now U.S. Pat. No. 6,337,502, issued Jan. 8, 2002.
However, in NROM devices, yet another problem may occur, wherein excess charge may accumulate along the edges of word lines. The excess charge is not uniform, and increases the threshold voltage Vt of the cell. The increase in threshold voltage being non-uniform across the device width, may degrade the reliability and endurance of the cell. In NROM cells, programmed bits in the charge-trapping nitride layer are generally erased by hot hole injection. However, hot hole injection may only erase charge next to the source/drain junctions. The charge along the word line edge, far from the source/drain junctions, may not generally be erased. It would therefore be desirable to prevent UV photon-induced charge effect in the word-line edges of NROM devices.
The present invention seeks to provide methods and apparatus for protecting against plasma-induced damage to semiconductor circuits. The invention may be used in any non-volatile memory device, particularly a memory device with a non-conducting charge layer. The invention will be described with reference to an NROM device, although it is understood that the invention is not limited to NROM devices.
In accordance with a preferred embodiment of the present invention, a protective layer is formed in the NROM device over a polycide structure (e.g., a word line). The protective layer may comprise an ultraviolet absorber, e.g., a nitride layer. Nitride is a good absorber of UV energy, and accordingly may prevent UV photons from the plasma etching from inducing stress in the polysilicon layer or gate stress in an oxide-nitride-oxide (ONO) layer. One preferred nitride comprises a thick silicon-rich silicon nitride alloy. Additionally or alternatively, the protective layer may comprise a layer of highly resistive undoped polysilicon.
There is thus provided in accordance with a preferred embodiment of the present invention a method for protecting a non-volatile memory device, the method including forming a non-volatile memory device including a polycide structure formed over a non-conducting charge trapping layer, and forming a protective layer over at least a portion of the polycide structure, the protective layer being adapted to absorb electromagnetic wave energy having a wavelength shorter than visible light.
There is also provided in accordance with a preferred embodiment of the present invention a non-volatile memory device including a polycide structure formed over a non-conducting charge trapping layer, and a protective layer formed over at least a portion of the polycide structure, the protective layer being adapted to absorb electromagnetic wave energy having a wavelength shorter than visible light.
In accordance with a preferred embodiment of the present invention the protective layer includes an ultraviolet absorber.
Further in accordance with a preferred embodiment of the present invention the protective layer includes a nitride layer.
Still further in accordance with a preferred embodiment of the present invention the nitride layer includes a silicon-rich silicon nitride alloy.
In accordance with a preferred embodiment of the present invention the nitride layer includes Si3+xN4, wherein x greater than 0.
Further in accordance with a preferred embodiment of the present invention the nitride layer includes a hydrogenated silicon-rich silicon nitride alloy.
Still further in accordance with a preferred embodiment of the present invention the nitride layer includes an amorphous silicon-rich silicon nitride alloy.
In accordance with a preferred embodiment of the present invention the protective layer includes a nitride layer with a thickness of 50-1000xc3x85.
Further in accordance with a preferred embodiment of the present invention the protective layer includes a layer of resistive undoped polysilicon.
Still further in accordance with a preferred embodiment of the present invention the protective layer of undoped polysilicon includes a resistivity of at least 1 Gxcexa9.
In accordance with a preferred embodiment of the present invention the protective layer of undoped polysilicon includes a thickness of 30-600 xc3x85.
Further in accordance with a preferred embodiment of the present invention at least one additional layer is formed over the protective layer.
Still further in accordance with a preferred embodiment of the present invention the at least one additional layer includes at least one of a layer of undoped glass, a layer of doped glass, and a metal layer.
In accordance with a preferred embodiment of the present invention the polycide structure includes a polysilicon layer and a metal silicide film.
Further in accordance with a preferred embodiment of the present invention the polysilicon layer includes a polycrystalline silicon (polysilicon). The polysilicon layer may or may not be doped with a dopant.
Still further in accordance with a preferred embodiment of the present invention the metal silicide film includes at least one of a tungsten silicide film and a titanium silicide film.
In accordance with a preferred embodiment of the present invention the non-volatile memory device includes a nitride, read only memory (NROM) device, and the non-conducting charge trapping layer includes a nitride charge trapping layer.